1. Field of the Invention
The present invention relates to a semiconductor integrated circuit. More particularly, it is suitable for a CMOS semiconductor integrated circuit suited to implement a high-speed operation with a low electric power. In particular, it relates to a semiconductor integrated circuit which can be implemented with a small area and without increasing the number of photomasks.
2. Description of the Prior Art
Conventionally, in order to implement the high-speed operation with the low electric power, there has been proposed the following method. Electric potentials of substrates of NMOS and PMOS (i.e. P-well and N-well) in a CMOS integrated circuit are controlled at the time of operation or standby, and thus the threshold values are set to be the optimum values for the low voltage operation. For example, in Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, pp. 166-167, the following method has been presented. P-well and N-well electrodes are put far from transistors made in the respective wells.
The higher the transistor is operated, the larger the substrate current generated from the transistor during the operation becomes. Accordingly, except when the integrated circuit is operated at a lower speed anyway, at the time of the high-speed operation, the well potential at transistor position differs from the well potential at electrode position. This makes it impossible to obtain an optimum value for the well potential.
Assuming that the substrate current from each transistor is equal to 1 xcexcA and 1000 units of transistors are operated simultaneously, the summation of the substrate currents becomes equal to 1 mA. Thus, if a resistance of each well is assumed to be 1 Kxcexa9, the resultant potential drop becomes equal to 1V. In spite of the fact that, judging from the present actual circumstance of the integrated circuit, these values are really ordinary and commonplace numerals, they bring about the potential variation of 1V. This potential variation gives rise to a variation of about 0.1 V to 0.3 V in the threshold voltage. Namely, there occurs the difference of such magnitude in the threshold value between the transistor in the proximity of the extracted electrode position and the transistor at the considerable distance therefrom. This condition causes the difference in the characteristics between both of the transistors, making it absolutely and utterly impossible to implement the high-speed operation.
Meanwhile, there has been known a method in which a line for providing a well potential is wired together with a power line and a ground line. In this case, the line permits the well potential to be extracted firmly and securely, thereby making the well potential remain constant regardless of the position. At this time, however, the layout of the both lines must be performed on an identical plane, which has necessitated a wide area.
Also, JP-A-10-154756 discloses a method in which a well potential line is wired with a diffusion layer and a power line is wired with a metal line layer. Unfortunately, the diffusion layer has a sheet resistance of about 10 xcexa9 even when a silicide is employed. This condition has increased a resistance of the line itself, placing a certain restriction onto the effect.
A problem that the present invention aims at solving is to implement a CMOS integrated circuit, which is allowed to operate at a high-speed with a low electric power by controlling a substrate bias, with a small area and without using extra photomasks.
In order to solve the above-described problem, in the present invention, a metal embedded in a contact hole is used as a line. For this purpose, contact holes having various types of configurations are formed. For example, a contact hole having a long and slim configuration is formed so as to electrically connect objects positioned away from each other. Even if a first metal line layer is made thinner or a metal such as tungsten with a comparatively high resistance is employed, the metal embedded in the contact hole is used as needed, thereby lowering and compensating for the high resistance resulting from the employment of the first metal line layer or tungsten. This compensation makes it possible to prevent the characteristic deterioration in the integrated circuit without increasing the number of the photomasks.
Moreover, the first metal line layer or the above-described metal embedded in the contact hole is used as the line for the well potential. Then, a second metal line layer is used as the line for the power supply or the ground potential, and the line for the power supply or the ground potential is wired in such a manner as to cover the metal line layer for the well potential. This makes it possible to form, while preventing increase in an area of the cell, a CMOS integrated circuit the substrate potential of which can be controlled. Also, at this time, a low resistance metal such as copper is used as the second metal line layer. This lowers a resistance of the power supply even further, resulting in an effect of enhancing the performance.
Also, the use of the above-described configuration of the lines makes the following possible. When DRAM cells are placed on the same chip, a bit line of the DRAM having a thin film thickness and a high resistance is made identical to the first metal line layer in the CMOS circuit. This condition permits the performances of the DRAM and CMOS circuit to be enhanced without increasing the number of the photomasks.
Explaining another aspect of the present invention, an integrated circuit device comprises: a MIS transistor formed in a substrate; a first line layer formed on the substrate; a second line layer formed on the first line layer; and a contact hole for electrically connecting two of a source, gate and drain of the MIS transistor, the first line layer and the second line layer, wherein when an X-Y plane is assumed on a surface of the substrate, configuration of projection onto the X-Y plane of the source, gate and drain of the MIS transistor, the first line layer or the second line layer which are connected by the contact hole has a non-overlapped portion.
Also, in another aspect, an integrated circuit device comprises: a MIS transistor formed in a substrate; a first line layer formed on the substrate; a second line layer formed on the first line layer; and a contact hole for electrically connecting two of a source, gate and drain of the MIS transistor, the first line layer and the second line layer, wherein when an X-Y plane is assumed on a surface of the substrate, configuration of projection onto the X-Y plane of contact portions at which said two of the source, gate and drain of the MIS transistor, the first line layer and the second line layer are connected by the contact hole has a non-overlapped portion.
Various types of conductors are embedded into the contact holes, thereby allowing the resistance to be adjusted. The first and second line layers are formed as metal line layers, thereby allowing the resistances to be lowered.
Also, an integrated circuit device comprises: a diffusion layer formed in a substrate; an intermediate layer formed on the substrate; a line layer formed on the intermediate layer; and a contact hole formed in the intermediate layer for electrically connecting the diffusion layer to the line layer, wherein when an X-Y plane is assumed on a surface of the substrate, configuration of projection onto the X-Y plane of a contact portion of the diffusion layer and the contact hole and configuration of projection onto the X-Y plane of a contact portion of the line layer and the contact hole have non-overlapped portions.
Also, an integrated circuit device comprises: a first line layer formed on a substrate; an intermediate layer formed on the first line layer; a second line layer formed on the intermediate layer; and a contact hole formed in the intermediate layer for electrically connecting the first line layer to the second line layer, wherein when an X-Y plane is assumed on a surface of the substrate, configuration of projection onto the X-Y plane of a contact portion of the first line layer and the contact hole and configuration of projection onto the X-Y plane of a contact portion of the second line layer and the contact hole have non-overlapped portions.
Also, in another aspect, an integrated circuit device comprises: a MIS transistor formed in a substrate; a first metal line layer formed on the substrate; and a second metal line layer formed on the first metal line layer, wherein at least a part of a power line connected to a source/drain channel in the MIS transistor is constituted by the second metal line layer; at least a part of a well potential line for controlling a well potential of the MIS transistor is constituted by the first metal line layer; and at least a part of the power line overlaps with at least a part of the well potential line.
Also, making the power line overlap with the well potential line completely allows an area of the element to be reduced. It is required to cause a comparatively large electric power to flow through the power line. For this reason, it is desirable that the width of the power line should be greater than that of the well potential line. For the reason similar to this, it is desirable that the first metal line layer should be composed of a metal the main constituent of which is tungsten and the second metal line layer should be composed of a metal the main constituent of which is copper with a low resistance. Also, the first metal line layer may be configured to be thinner than the second metal line layer. Also, a contact hole is formed in an intermediate layer between the substrate and the first metal line layer in such a manner that the contact hole overlaps with the first metal line which constitutes a part of the well potential line. As the result, the contact hole as well constitutes a part of the well potential line, which makes it possible to lower a resistance of the well potential line. At this time, making the first metal line overlay the contact hole allows the area of the element to be reduced.
Also, in another aspect, an integrated circuit device comprises: a MIS transistor formed in a substrate; a first metal line layer formed on the substrate; an intermediate layer between the substrate and the first metal line layer; and a second metal line layer formed on the first metal line layer, wherein at least a part of a power line connected to a source/drain channel in the MIS transistor is constituted by the second metal line layer; at least a part of a well potential line for controlling a well potential of the MIS transistor is constituted by a conductor which is formed within a contact hole formed in the intermediate layer; and the power line overlaps with the contact hole. At this time, the width of the power line can be made greater than that of the contact hole.
Also, in another aspect, an integrated circuit device comprises: a MIS transistor formed in a substrate; a first metal line layer formed on the substrate; and a second metal line layer formed on the first metal line layer, wherein at least a part of a power line connected to a source/drain channel in the MIS transistor is constituted by the second metal line layer; at least a part of a well potential line for controlling a well potential of the MIS transistor is constituted by the first metal line layer; the first metal line layer is formed of tungsten as a main constituent; and the second metal line layer is formed of copper as a main constituent.
In another aspect, an integrated circuit device comprises: a MIS transistor formed in a substrate; a memory cell for storing data; a first metal line layer formed on the substrate; and a second metal line layer formed on the first metal line layer, wherein at least a part of a power line connected to a source/drain channel in the MIS transistor is constituted by the second metal line layer, at least a part of a well potential line for controlling a well potential of the MIS transistor is constituted by the first metal line layer; and at least a part of a bit line for transmitting an input/output data signal to/from the memory cell is constituted by the first metal line layer.
Also, when forming an integrated circuit device in which a memory and a logical circuit are mixed, it is desirable that the integrated circuit device comprises: a MIS transistor formed in a substrate; a memory cell for storing data; a first line layer a main constituent of which is tungsten; and a second metal line layer a main constituent of which is copper, wherein at least a part of a power line connected to a source/drain channel in the MIS transistor is constituted by the second metal line layer; at least a part of a well potential line for controlling a well potential of the MIS transistor is constituted by the first metal line layer; and at least a part of a bit line for transmitting an input/output data signal to/from the memory cell is constituted by the first metal line layer.
As another aspect in this case, an integrated circuit device comprises: a MIS transistor formed in a substrate; a memory cell for storing data; a first metal line layer which is formed on the substrate and a main constituent of which is tungsten; and a second metal line layer which is formed on the first metal line layer and a main constituent of which is copper, wherein at least a part of a power line connected to a source/drain channel in the MIS transistor is constituted by the second metal line layer; and at least a part of a bit line for transmitting an input/output data signal to/from the memory cell is constituted by the first metal line layer.
Here, at least the part of the well potential line for controlling the well potential of the MIS transistor may be constituted by the first metal line layer. Also, in a preferred concrete embodiment, the memory cell is a DRAM cell. Thus, a capacitor in the DRAM cell is located between the first metal line layer and the second metal line layer. More concretely, a gate electrode layer is located between the substrate and the first metal line layer.
Also, as a modification example, an integrated circuit device comprises a contact hole for selecting two of a substrate, a first metal line layer, a second metal line layer and a gate electrode layer as a first connection object and a second connection object so as to connect the first connection object to the second connection object, wherein when an X-Y plane is assumed on a surface of the substrate, projection onto the X-Y plane of a contact surface of the first connection object and the contact hole has a portion at which said projection does not overlap with a mapping onto the X-Y plane of a contact surface of the second connection object and the contact hole.
The foregoing and other objects, advantages, manner of operation and novel features of the present invention will be understood from the following detailed description when read in connection with the accompanying drawings.